Simulation of the PCI-Current Limit Logic of dsPIC33CH

INTRODUCTION

The dsPIC33CH IC has a PCI CL (PWM Control Input-Current Limit) Logic that is use for Current Mode Controlled Converter. An equivalent circuit in LTSPICE is simulated to gain better insights of this logic system. The simulated circuit is based on actual circuit values in the DM330038 dsPIC33CH Curiosity Development Board.

SIMPLIFIED BUCK CONVERTER SCHEMATIC

Below is a simplified schematic of the current mode controlled buck converter of the board with connection to the dsPIC33CH IC. The PWM duty cycle is fixed at usually 95%. the PCI CL purpose is to override (block or truncate) the PWM output everytime the output of the current sense circuit exceeds the reference value. The reference value is an analog voltage generated from the PID by a DAC.

From above figure, we can see that the PCI-CL is part of the PWM Module of the IC.

PCI DIAGRAM

Below is the diagram of the PCI from DS70005320B document.

The table below are the register values from above diagram that are needed to configure in order for the PCI to become a current limit logic for the current mode converter:

By using the values of the registers in the above table. The PCI logic is simplified to the diagram below.

The Leading Edge Blanking (LEB) is a counter circuit that is synchronized with the PWM output and becomes Active after the PWM output becomes high and then resets/stop after the PWM becomes low. The purpose of the LEB is to ignore switching transients. 

The Auto-Terminate is a logic circuit that detects falling signal of the comparator output and is reset every start of PWM cycle.

LTSPICE SIMULATION CIRCUIT

Below is the LTSPICE schematic for the simulation of this simplfied current limit logic with the comparator, pwm and power circuit. The Analog Comparator Reference is fixed at 0.75 for debugging purposes. The ADC and PID are not included in this simulation for simplicity. The LEB is replaced by a DFLOP instead of a counter for shorter simulation time. The output POLARITY is inverted because Power MOSFET Q6 needs 0V to turn on.

LTSPICE SIMULATION RESULT

Below are some of the waveforms from the result of the simulation. The first plot pane from the top shows the PWM output running at 95% duty cycle. The 2nd plot pane from the top shows PCI_Active signal which blocks the PWM output. The truncated output PWM7H is shown in the third plot from the top. The red waveform Ix(Q6:S) is the current flow in power MOSFET Q6. The 4th plot from the top shows the momentary pulse from the comparator output PCI_SOURCE when the sense current RA3_ISENSEH reached the reference voltage DAC.

LTSPICE Simulation Files: DSPIC33 PCI Current Limit Simulation LTSPICE